Technical Note
3/18
www.rohm.com
2009.08 - Rev.A
?2009 ROHM Co., Ltd. All rights reserved.
BD9153MUV
?SPAN class="pst BD9153MUV-E2_2471427_7">Block Diagram, Application Circuit
?SPAN class="pst BD9153MUV-E2_2471427_7">Pin No. & function table
Pin No. Pin name
Function
Pin No. Pin name
Function
1 PGND2 Nch FET Source pin (2CH)
13 GATE Gate drive pin
2 PVCC2 Pch FET Source pin (2CH)
14 FB3 Output Voltage3 detector pin
3 PVCC2 Pch FET Source pin (2CH)
15 AVCC AVCC power supply input pin
4 PVCC1 Pch FET Source pin (1CH)
16 DET Voltage detector pin
5 PVCC1 Pch FET Source pin (1CH)
17 RST RST signal output pin
6 PGND1 Nch FET Source pin (1CH)
18 AGND Ground
7 PGND1 Nch FET Source pin (1CH)
19 ITH2 GmAmp2 output pin
8 SW1 SW pin (1ch)
20 FB2 Output Voltage2 detector pin
9 SW1 SW pin (1ch)
21 EN Enable pin (High Active)
10 VS Discharge function pin
22 SW2 SW pin (2ch)
11 FB1 Output Voltage1 detector pin
23 SW2 SW pin (2ch)
12 ITH1 GmAmp1output pin
24 PGND2 Nch FET Source pin (2ch)
Fig.2 BD9153MUV Block Diagram
Fig.1 BD9153MUV TOP View
(Unit : mm)
2.4?.1
C0.2
0.5
0.75
1
6
7
12
13
18
19
24
4.0?/SPAN>0.1
0.25
+0.05
-0.04
0.08 S
S
D9153
Lot No.
Current
Sense/
Protect
+
Driver
Logic
Soft
Start1
Slope1
R
S
Q
OSC
VREF
SCP/
TSD
SCP2
Current
Sense/
Protect
+
Driver
Logic
Soft
Start2
Slope2
R
S
Q
SCP1
CLK2
Gm Amp
Current
Comp
Gm Amp
Current
Comp
CLK1
CLK2
UVLO1
EN
PVCC
SW1
PGND2
SW2
ITH1
ITH2
GND
PVCC
PGND1
UVLO2
SCP3
GATE
FB3
VS
DET
RST
Timer
Soft
Start1
ITH1
FB1
SCP/TSD
UVLO1
FB2
FB1
OUT1
OUT2
OUT3
OUT1
OUT1
OUT2
PGND1
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